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| target specification this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. december 2006 rev 1 1/38 1 STA2416 bluetooth? baseband wi th integrated flash features bluetooth? specification compliance: v1.1 and v1.2 sw compatible with stlc2416 2 layer class 4 pcb compatible ? point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability asynchronous connection oriented (acl) logical transport link synchronous connection oriented (sco) links: 2 simultaneous sco channels supports pitch-period error concealment (ppec) ? improves speech quality in the vicinity of interference ? improves coexistence with wlan ? works at receiver, no bluetooth implication adaptive frequency hopping (afh): hopping kernel, channel assessment as master and as slave faster connection: interlaced scan for page and inquiry scan, first fhs without random backoff, rssi used to limit range extended sco (esco) links standard bluerf bus interface qos flush clock support ? system clock input: any integer value from 12 to 33 mhz ? lpo clock input at 3.2 and 32 khz or via the embedded 32 khz crystal oscillator cell arm7tdmi 32-bit cpu memory ? integrated 4 mbit flash ? 64 kbyte on-chip ram ? 4 kbyte on-chip boot rom low power architecture with sleep mode hw support for packet types ? acl: dm1, 3, 5 and dh1, 3, 5 ? sco: hv1, 3 and dv ?esco: ev3, 5 communication interfaces ? synchronous serial interface, supporting up to 32-bit data ? two enhanced 16550 uarts with 128-byte fifo depth ? 12 mbps usb interface ? fast master i 2 c bus interface ? multi slot pcm interface ? 15 programmable gpios ? 2 external interrupts and various interrupt possibilities throug h other interfaces 32 khz clock out efficient support for wlan coexistence ciphering support for up to 128-bit key receiver signal strength indication (rssi) support for power-controlled links separate control for external power amplifier (pa) for class1 power support software support: low level (up to hci) stack or embedded stack with profiles ? support of uart and usb hci transport layers lfbga120 (10x10x1.4mm) part number package packing STA2416 lfbga120 (10x10x1.4mm) tube www.st.com
contents STA2416 2/38 contents 1 application features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 block diagram and pins descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 pin description and assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.1 specifications for 3.3 v i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.2 specifications for 1.8 v i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 baseband 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 baseband 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 integrated flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 flash signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 general specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 slow clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 boot procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 master reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 interrupts/wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 v1.2 detailed functionality - extended sco . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 v1.2 detailed functionality - adaptive frequency hopping . . . . . . . . . . . . . 23 STA2416 contents 3/38 6.8 v1.2 detailed functionality - faster connection . . . . . . . . . . . . . . . . . . . . . 23 6.9 v1.2 detailed functionality - quality of service . . . . . . . . . . . . . . . . . . . . . 24 6.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10.1 sniff or park . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10.2 inquiry/page scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10.3 no connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10.4 active link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.11 sw initiated low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.12 bluetooth? - wlan coexistence in collocated scenario . . . . . . . . . . . . . 25 6.12.1 algorithm 1: pta (packet traffic arbitration) . . . . . . . . . . . . . . . . . . . . . . 26 6.12.2 algorithm 2: wlan master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.12.3 algorithm 3: bluetooth? master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.12.4 algorithm 4: two-wire mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.12.5 algorithm 5: alternating wireless medium access (awma) . . . . . . . . . . 27 7 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 uart interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.1 feature description: agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.2 feature description: 32-bit spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6 rf interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 pcm voice interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 hci uart transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 uart settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 hci usb transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 class1 power support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 list of tables STA2416 4/38 list of tables table 1. pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. lvttl dc input specification (3v STA2416 list of figures 5/38 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin out (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4. esco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. afh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. algorithm 1: pta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. algorithm 2: wlan master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. algorithm 3: bluetooth? master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. agilent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. 32-bit spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. pcm (a-law, m-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 figure 13. linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14. pcm interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 15. uart transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16. lfbga120 (10x10x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . 36 application features STA2416 6/38 1 application features typical applications in which the STA2416 can be used are: cable replacement portable computers, pda handheld data transfer devices computer peripherals other type of devices that require the wireless communication provided by bluetooth? sw host for stlc2500x st single chip audio application includes: ? headset ? headphone ? wireless speakers ? wireless transmitter 2 description the STA2416 from stmicroelectronics is a bluetooth? baseband controller with integrated 4-mbit flash memory. together with a bluetoot h? radio this product offers a compact and complete solution for short-range wireless connectivity. it incorporates all the lower layer functions of the bluetooth? protocol. the microcontroller allows the support of all data packets of bluetooth? in addition to voice. the embedded controller can be used to run the bluetooth? protocol and application layers if required. the software is located in the integrated flash memory. STA2416 block diagram and pins description 7/38 3 block diagram and pins description 3.1 block diagram figure 1. block diagram radio i/f bluetooth core arm7 tdmi apb bridge interrupt controller timer start detect uart fifo system control emi data(0..15) addr(0..19) csn(0) wrn rdn nw ng ne addr(1..18) data(0..15) 4mbit flash uart uart 100nf 100nf 22pf y2 32khz (*) if a low-power clock is available, it can be connected to the lpoclkp pin in stead of using a crystal (**) for device testing only (should not be connected in the application. 22pf gpio boot rom d m a ram lpo 13 4 rf bus pcm ext._int1/2 usb i 2 c spi gpio(0..9)(11...15) uart2 uart1 v dd nreset sys_clk_req lpoclkp lpoclkn vddpll spi i 2 c usb pcm 2 2 4 1 5 jtag xin boot csn(1..2) rdn/ng nrp nwp csn(0) ne addr (0,2,17,18,19) data(0..15) 2 1 1 1 20 18 16 16 15 8 2 2 2 1 1 5 d05au1623 v dd 100nf v ddio 100nf v ddio 100nf v dd (*) (**) 16 lpoclkout block diagram and pins description STA2416 8/38 3.2 pin description figure 2. pin out (top view) d05au1624 a b c d e f g h j k l m n p r t u v 14 13 12 11 18 17 16 15 10 9 8 7 6 5 4 3 2 1 i2c_ dat i2c_ clk pcm_ sync pcm_ a nreset nrp uart1_ rxd uart1_ txd usb_ dn uart2_ rxd uart2_ txd uart2_ i1 uart2_ o2 vddio vdd vss spi_ frm spi_ clk xin int2 int1 vddio n.c. vssio tck vssio tdo tms ntrst tdi btxen ne csn2 rdn/ng csn1 addr0 vddio sys_cl k_req brxen addr2 nwp vdd vss vpp ant_sw bpktcl btxd bpaen bdclk vddf bmosi brclk vssf addr17 vss n.c. vdd pcm_ clk pcm- b usb_ dp uart2_ i2 uart2_ o1 uart2_ io1 uart2_ io2 vssio brxd bmiso data3 data1 n.c. n.c. data0 addr19 vddq csn0 spi_rxd addr18 bsen bnden gpio3 gpio1 boot vss vdd data8 data7 data6 data5 data4 gpio12 gpio14 gpio15 ipio_clk_out gpio11 gpio13 gpio9 vddpll gpio8 gpio7 gpio6 gpio2 gpio0 vddio vsspll gpio4 vssio gpio5 lpo_ clk_n lpo_ clk_p data15 data14 data13 data12 data11 data10 data9 data2 vss vdd spi_txd STA2416 block diagram and pins description 9/38 3.3 pin description and assignment ta bl e 1 shows the pin list of the STA2416. there are 91 functional pins of which 25 are used for device testing only (should not be connected in the application) and 24 supply pins. the column ?pu/pd? shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. this cannot replace an external pull-up/down. the pads are grouped according to two differen t power supply values, as shown in column vdd: v1 for 3.3 v typical 2.7 - 3.6 v range v2 for 1.8 v typical 1.55 - 1.95 v range finally the column ?dir? describes the pin directions: i for inputs o for outputs i/o for input/outputs o/t for trim-state outputs ( table 1. pin list name pin # description dir pu/pd vdd pad clock and test pins in b18 system clock i v1 cmos, 3.3v ttl compatible schmidt trigger nearest a18 reset i unripe a17 flash reset i v2 nwp h3 flash write protect i v2 cmos 1.8v sys_clk_req c18 system clock request i/o v1 cmos, 3.3v ttl compatible, 2ma tri-state slew rate control lpo_clk_p v9 low power oscillator + /slow clock input i v2 lpo_clk_n v10 low power oscillator - o lpo_clk_out r18 32mhz clock out o - v1 int1 c14 external interrupt used also as external wakeup i (1) v1 cmos, 3.3v ttl compatible schmidt trigger int2 c15 second external interrupt i (1) boot t10 select external boot from emi or internal from rom i (1) v2 cmos 1.8v block diagram and pins description STA2416 10/38 spi interface spi_frm a2 synchronous serial interface frame sync i/o v1 cmos, 3.3v ttl compatible, 2ma tri-state slew rate control schmidt trigger spi_clk a1 synchronous serial interface clock i/o spi_txd b1 synchronous serial interface transmit data o/t v1 cmos, 3.3v ttl compatible, 2ma slew rate control spi_rxd c1 synchronous serial interface receive data i (1) v1 cmos, 3.3v ttl compatible schmidt trigger uart interface uart1_txd a15 uart1 transmit data o/t v1 cmos, 3.3v ttl compatible, 2ma slew rate control uart1_rxd a16 uart1 receive data i (2) v1 cmos, 3.3v ttl compatible schmidt trigger uart2_o1 c7 uart2 modem output o v1 cmos, 3.3v ttl compatible, 2ma slew rate control uart2_o2 a6 uart2 modem output o/t v1 cmos, 3.3v ttl compatible, 2ma slew rate control uart2_i1 a7 uart2 modem input i (2) v1 cmos, 3.3v ttl compatible uart2_i2 c8 uart2 modem input i (2) v1 uart2_io1 c6 uart2 modem input/output i/o (2) v1 cmos, 3.3v ttl compatible, 2ma tri-state slew rate control uart2_io2 c5 uart2 modem input/output i/o (2) v1 uart2_txd a8 uart2 transmit data o/t v1 cmos, 3.3v ttl compatible, 2ma slew rate control uart2_rxd a9 uart2 receive data i (2) v1 cmos, 3.3v ttl compatible i 2 c interface i 2 c_dat a14 i 2 c data pin i/o (3) v1 cmos, 3.3v ttl compatible, 2ma tri-state slew rate control i 2 c_clk a13 i 2 c clock pin i/o (3) v1 table 1. pin list (continued) name pin # description dir pu/pd vdd pad STA2416 block diagram and pins description 11/38 usb interface usb_dn a10 usb - pin (needs a series resistor of 27 ? 5%) i/o (1) v1 usb_dp c9 usb + pin (needs a series resistor of 27 ? 5%) i/o (1) v1 gpio interface gpio0 v11 gpio port 0 i/o pu v1 cmos, 3.3v ttl compatible, 4ma tri-state slew rate control gpio1 t11 gpio port 1 i/o pu gpio2 v12 gpio port 2 i/o pu gpio3 t12 gpio port 3 i/o pu v1 cmos, 3.3v ttl compatible, 4ma tri-state slew rate control schmidt trigger gpio4 v13 gpo port 4 i/o pu v1 cmos, 3.3v ttl compatible, 4ma trim-state slew rate control gpio5 v14 gpo port 5 i/o pu gpio6 v16 gpo port 6 i/o pu gpio7 v17 gpo port 7 i/o pu gpio8 v18 gpo port 8 i/o pu v1 cmos, 3.3v ttl compatible, 2ma trim-state slew rate control gpio9 u18 gpo port 9 i/o pu gpio11 t18 gpo port 11 i/o pu gpio12 p18 gpo port 12 i/o pu gpio13 t16 gpo port 13 i/o pu gpio14 p16 gpo port 14 i/o pu gpio15 r16 gpo port 15 i/o pu table 1. pin list (continued) name pin # description dir pu/pd vdd pad block diagram and pins description STA2416 12/38 jtag interface entrust f18 jtag pin i pd v1 cmos, 3.3v ttl compatible tko d18 jtag pin i (1) v1 cmos, 3.3v ttl compatible schmidt trigger tams e16 jtag pin i pu v1 cmos, 3.3v ttl compatible ti f16 jtag pin i pu do e18 jtag pin (should be left open) o/t v1 cmos, 3.3v ttl compatible, 2ma slew rate control pcm interface pecan a11 pcm data i/o pd v1 cmos, 3.3v ttl compatible, 2ma trim-state slew rate control bitmap c10 pcm data i/o pd pcm_sync a12 pcm 8khz sync i/o pd pcm_clk c11 pcm clock i/o pd v1 cmos, 3.3v ttl compatible, 2ma tri-state slew rate control schmidt trigger radio interface brclk l18 transmit clock i (1) v1 cmos, 3.3v ttl compatible schmidt trigger brxd m18 receive data i bmiso m16 rf serial interface input data i (1) v1 cmos, 3.3v ttl compatible bnden n16 rf serial interface control o v1 cmos, 3.3v ttl compatible, 2ma slew rate control bmosi l16 rf serial interface output data o bdclk k16 rf serial interface clock o btxd k18 transmit data o bsen n18 synthesizer on o v1 cmos, 3.3v ttl compatible, 2ma slew rate control bpaen j16 open pll o brxen h18 receive on o btxen g18 transmit on o bpktctl j18 packet on o ant_sw h16 antenna switch o v1 cmos, 3.3v ttl compatible, 8ma slew rate control table 1. pin list (continued) name pin # description dir pu/pd vdd pad STA2416 block diagram and pins description 13/38 power supply vsspll t15 pll ground vddpll v15 1.8v supply for pll vdd a4 1.8v digital supply vdd f1 1.8v digital supply vdd j1 1.8v digital supply vdd u1 1.8v digital supply vdd t8 1.8v digital supply vddf k3 1.8v digital supply flash vddq m3 1.8v i/o?s supply flash vpp j3 12v fast program supply flash vddio c13 3.3v i/o?s supply vddio a5 3.3v i/o?s supply vddio t13 3.3v i/o?s supply vddio g16 3.3v i/o?s supply vss a3 digital ground vss g1 digital ground vss k1 digital ground vss v1 digital ground vss t9 digital ground vssf l3 digital ground flash vssio c12 i/o?s ground vssio c4 i/o?s ground vssio t14 i/o?s ground vssio d16 i/o?s ground to be connected together on the pcb ne d3 flash chip enable i csn0 e3 external chip select bank 0 o table 1. pin list (continued) name pin # description dir pu/pd vdd pad block diagram and pins description STA2416 14/38 test only (do not connect) rdn/ng c3 external read o v2 cmos 1.8v 4ma slew rate control csn1 d1 external chip select bank 1 o csn2 e1 external chip select bank 2 o addr0 f3 external address bit 0 o addr2 h1 external address bit 2 o addr17 l1 external address bit 17 o addr18 m1 external address bit 18 o addr19 n1 external address bit 19 o data0 p1 external data bit 0 i/o pd data1 r1 external data bit 1 i/o pd data2 t1 external data bit 2 i/o pd data3 r3 external data bit 3 i/o pd data4 t3 external data bit 4 i/o pd data5 t4 external data bit 5 i/o pd data6 t5 external data bit 6 i/o pd v2 cmos 1.8v 4ma slew rate control data7 t6 external data bit 7 i/o pd data8 t7 external data bit 8 i/o pd data9 v2 external data bit 9 i/o pd data10 v3 external data bit 10 i/o pd data11 v4 external data bit 11 i/o pd data12 v5 external data bit 12 i/o pd data13 v6 external data bit 13 i/o pd data14 v7 external data bit 14 i/o pd data15 v8 external data bit 15 i/o pd not connected n.c. c16, g3, n3, p3 not connected 1. should be strapped to vssio if not used 2. should be strapped to vddio if not used 3. must have a 10 kohm pull-up table 1. pin list (continued) name pin # description dir pu/pd vdd pad STA2416 quick reference data 15/38 4 quick reference data 4.1 absolute maximum ratings operation of the device beyond these conditions is not guaranteed. sustained exposure to these limits will adversely affect device reliability. 4.2 operating ranges operating ranges define the limits for functional operation and parametric characteristics of the device. functionality outside these limits is not implied. table 2. absolute maximum ratings symbol conditions min max unit v dd supply voltage baseband core v ss ? 0.5 2.5 v v ddf supply voltage flash v ss ? 0.5 2.5 v v pp fast program voltage v ss ? 0.5 13 v v ddio supply voltage baseband i/o 4 v v ddq supply voltage flash i/o v ss ? 0.5 2.5 v v in input voltage on any digital pin (excluding flash input pins) v ss ? 0.5 v ddio + 0.3 v t stg storage temperature -55 +150 c t lead lead temperature < 10s +240 c table 3. operating ranges symbol conditions min typ max unit v dd supply voltage baseband core and emi pads 1.55 1.8 1.95 v v ddf supply voltage flash 1.55 1.8 1.95 v v ddio supply voltage digital i/o 2.7 3.3 3.6 v v ddq supply voltage flash i/o (v ddq v ddf ) 1.55 1.8 1.95 v t amb operating ambient temperature -40 +85 c quick reference data STA2416 16/38 4.3 i/o specifications depending on the interface, the i/o voltage is typical 1.8 v (interface to the flash memory) or typical 3.3 v (all the other interfaces). these i/os comply with the eia/jedec standard jesd8-b. 4.3.1 specifications for 3.3 v i/os note: x is the source/sink curren t under worst-case cond itions according to the drive capability. (see table 1: pin list on page 9 for the value of x). 4.3.2 specifications for 1.8 v i/os note: x is the source/sink curren t under worst-case cond itions according to the drive capability. (see table 1: pin list on page 9 for the value of x). table 4. lvttl dc input specification (3v functional description STA2416 18/38 5 functional description 5.1 baseband wlan coexistence. see also section 6.12: bluetooth? - wlan coexistence in collocated scenario . 5.1.1 baseband 1.1 features the baseband is based on ericsson technology licensing baseband core (ebc) and it is compliant with the bluetoo th? specification 1.1. point to multipoint (up to 7 slaves). asynchronous connection less (acl) link support giving data rates up to 721 kbps. synchronous connection oriented (sco) link with support for 2 voice channels over the air interface. flexible voice format to host and over the air (cvsd, pcm 13/16 bits, a-law, -law). hw support for packet types: dm1, 3, 5; dh1, 3, 5; hv1, 3; dv. scatternet capabilities (master in one piconet and slave in the other one; slave in two piconets). all scatternet v.1.1 errata supported. ciphering support up to 128 bits key. paging modes r0, r1, r2. channel quality driven data rate. full bluetooth software stack available. low level link controller. 5.1.2 baseband 1.2 features the baseband part is also compliant with the bluetooth specification 1.2. extended sco (esco) links: supports ev3 and ev5 packets. see also section 6.6: v1.2 detailed functionality - extended sco on page 22 . adaptive frequency hopping (afh): hopping kernel, channel assessment as master and as slave. see also section 6.7: v1.2 detailed functionality - adaptive frequency hopping on page 23 . faster connection: interlaced scan for page and inquiry scan, answer fhs at first reception, rssi used to limit range. see also section 6.8: v1.2 deta iled functionality - faster connection on page 23 . qos flush. see also section 6.9: v1.2 detailed functionality - quality of service on page 24 . synchronization: the local and the master bt clock are available via hci commands for synchronization of parallel applications on different slaves. l2cap flow and error control. lmp improvements. lmp sco handling. parameter ranges update. STA2416 functional description 19/38 5.2 integrated flash memory features: 4-mbit size eight parameter blocks of 4 kword (top configuration) seven main blocks of 32 kword 120 ns access time see the datasheet for the standalone product m28r400ct for detailed information. figure 3. block addresses 5.2.1 flash signal descriptions write protect (nwp) write protect is an input that gives an additional hardware protection for each block. when write protect is 0.4v the lock-down is enabled and the protection status of the flash blocks cannot be changed. when write protect is (vddq - 0.4v), the lock-down is disabled and the flash memory blocks can be locked or unlocked. reset (nrp) the reset input provides a hardware reset of the memory. when reset is 0.4v, the memory is in reset mode: the outputs are high impedant and the current consumption is minimized. after reset all blocks are in locked state. when reset is (vddq - 0.4v), the device is in normal operation. exiting reset mode the device enters read array mode, but a negative transition of chip enable or a change of the address is required to ensure valid data outputs. 4 kwords 3ffff 3f000 32 kwords 0ffff 08000 32 kwords 07fff 00000 m28r400ct top boot block addresses 4 kwords 38fff 38000 32 kwords 30000 37fff total of 8 4 kword blocks total of 7 32 kword blocks functional description STA2416 20/38 vdd supply voltage (vddf) vdd provides the power supply to the internal core of the flash memory device. it is the main power supply for all operations (read, program and erase) vddq supply voltage (vddq) vddq provides the power supply to the i/o pins and enables all outputs to be powered independently from vddf. vddq can be tied to vddf or can use separate supply. vpp program supply voltage (vpp) vpp is both a control input and a power supply pin. the two functions are selected by the voltage range applied to the pin. the supply voltage vddf and the program supply voltage vpp can be applied in any order. if vpp is kept in a low voltage range (0 v to 3.6 v) vpp is seen as a control input. in this case a voltage lower than 1 v gives protection agains program or block erase, while 1.65 v < vpp < 3.6 v enables these functions. vpp is only sampled at the beginning of a program or block erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if vpp is in the range 11.4 v to 12.6 v it acts as a power supply pin. in this condition vpp must be stable until the program/erase algorithm is completed. vssf flash ground (vssf) vssf is the reference for all voltage measurements. address inputs (addr0-addr17), data input/output (data0-data15), chip enable (csn0), output enable (rdn/ng), write enable (wrn) these are connected to and controlled by the bluetooth? baseband controller. STA2416 general specification 21/38 6 general specification 6.1 system clock the STA2416 works with a single clock provided on the xin pin. the value of this external clock should be any integer value from 12 ? 33 mhz 20 ppm (overall). 6.1.1 slow clock the slow clock is used by the baseband as reference clock during the low power modes. the slow clock requires an accuracy of 250 ppm (overall). several options are foreseen in order to adjust the STA2416 behavior according to the features of the radio used. if the system clock (for example, 13 mhz) is not provided at all times (power consumption saving) and no slow clock is provided by the system, a 32 khz crystal must be used by the STA2416 (default mode). if the system clock (for example, 13 mhz) is not provided at all times (power consumption saving) and the system provides a slow clock at 32 khz or 3.2 khz, this signal is simply connected to the STA2416 (lpo_clk_p). if the system clock (for example, 13 mhz) is provided at all times, the STA2416 generates from the reference clock an internal 32 khz clock. this mode is not an optimized mode for power consumption. 6.2 boot procedure the boot code instructions are the first that arm7tdmi executes after a hw reset. all the internal device's registers are set to their default value. there are two types of boot: flash boot when boot pin is set to ?1? (connected to vdd), the STA2416 boots on its flash uart download boot from rom when boot pin is set to ?0? (connected to gnd), the STA2416 boots on its internal rom (needed to download the new firmware in the flash). when booting on the internal rom, the STA2416 will monitor the uart inte rface for approximately 1.4 second. if there is no request for code downloading during this period, the rom jumps to flash. 6.3 clock detection the STA2416 has an automatic slow clock frequency detection (32khz, 3.2khz or none). general specification STA2416 22/38 6.4 master reset when the device?s reset is held active (n reset is low), uart1_txd and uart2_txd are set to input state. when the nreset retu rns high, the device starts to boot. note: the device should be held in active reset for minimum 20 ms in order to guarantee a complete reset of the device. 6.5 interrupts/wake-up all gpios can be used both as external interrupt source and as wake-up source. in addition the chip can be woken-up by usb, uart1_rxd, uart2_rxd, int1, int2. 6.6 v1.2 detailed functi onality - extended sco user perspective - extended sco this function gives improved voic e quality since it enables the po ssibility to retransmit lost or corrupted voice packets in both directions. technical perspective - extended sco esco incorporates crc, negotiable data rate, negotiable retransmission window and multi-slot packets. retransmission of lost or corrupted packets during the retransmission window guarantees on-time delivery. figure 4. esco sco sco sco sco acl sco sco acl t esco retransmission window STA2416 general specification 23/38 6.7 v1.2 detailed functionalit y - adaptive frequency hopping user perspective - adaptive frequency hopping in the bluetooth? specification 1.1 the blue tooth devices hop in the 2.4 ghz band over 79-channels. since wlan 802.11 has become popular, there are specification improvements in the 1.2-sig spec for bluetooth where the bluetooth units can avoid the jammed bands and thereby provide an improved co-existence with wlan. technical perspective - adaptive frequency hopping figure 5. afh first the master and/or the slaves identify the jammed channels. the master decides on the channel distribution and informs the involved slaves. the master and the slaves, at a predefined instant, switch to the new channel distribution scheme. no longer jammed channels are re-inserted into the channel distribution scheme. afh uses the same hop frequency for transmission as for reception 6.8 v1.2 detailed function ality - faster connection user perspective - faster connection this feature gives the user about 65% faster connection on average when enabled compared to bluetooth? specification 1.1 connection procedure. technical perspective - faster connection the faster inquiry functionality is based on a removed/shortened random back off and also a new interlaced inquiry scan scheme. the faster page functionality is based on interlaced page scan. t wlan used frequency wlan used frequency t f f afh(79) afh(19 STA2416 general specification 25/38 6.10.2 inquiry/page scan when only inquiry scan or page scan is enab led, the STA2416 will go in sleep mode or deep sleep mode outside the receiver activity. the selection between sleep mode and deep sleep mode depend on the uart activity like in sniff or park. 6.10.3 no connection if the host places the uart in low power and there is no activity, then the STA2416 can be placed in deep sleep mode. 6.10.4 active link when there is an active link (sco or acl), the STA2416 cannot go in deep sleep mode whatever the uart state is. but the STA2416 baseband is made such that whenever it is possible, depending on the scheduled activity (number of link, type of link, amount of data exchanged), it goes in sleep mode. 6.11 sw initiated low power mode a wide set of wake up mechanisms are supported. 6.12 bluetooth? - wlan coexis tence in collocated scenario the coexistence interface uses four gpio pins, when enabled. bluetooth? and wlan 802.11 b/g technologies occupy the same 2.4 ghz ism band. STA2416 implements a set of mechanisms to avoid interference in a collocated scenario. the STA2416 supports five different algorithms in order to provide efficient and flexible simultaneous functionality between the two technologies in collocated scenarios. algorithm 1: pta (packet traffic arbitration) based coexistence algorithm defined in accordance with the ieee 802. 15.2 recommended practice. algorithm 2: the wlan is the master and it indicates to the STA2416 when not to operate in case of simultaneous use of the air interface. algorithm 3: the STA2416 is the master and it indicates to the wlan chip when not to operate in case of simultaneous use of the air interface. algorithm 4: two-wire mechanism. algorithm 5: alternating wireless medium access (awma), defined in accordance with the wlan 802.11 b/g technologies. the algorithm is selected via hci comman d. the default algorithm is algorithm 1. general specification STA2416 26/38 6.12.1 algorithm 1: pta (pac ket traffic arbitration) algorithm 1 is based on a bus connection between the STA2416 and the wlan chip. figure 6. algorithm 1: pta by using this coexistence interface it's possible to dynamically allocate bandwidth to the two devices when simultaneous operations are required while the full bandwidth can be allocated to one of them in case the other one does not require activity. the algorithm involves a priority mechanism, which allows pres erving the quality of certain types of link. a typical application would be to guarantee optimal quality to the bluetooth? voice communication while an intensive wlan communication is ongoing. several algorithms have been implemented in order to provide a maximum of flexibility and efficiency for the priority handling. those algorithms can be activated via specific hci commands. the combination of a time division multiplexing techniques to share the bandwidth in case of simultaneous operations and of the priority mechanism avoid the interference due to packet collision and it allows the maximization of the 2.4 ghz ism band width usage for both devices while preserving the quality of some critical types of link. 6.12.2 algorithm 2: wlan master in case the STA2416 has to cooperate, in a collocated scenario, with a wlan chip not supporting a pta based algorithm, it's possible to put in place a simpler mechanism. the interface is reduced to 1 line. figure 7. algorithm 2: wlan master when the wlan has to operate, it alerts high the rf_not_allowed signal and the STA2416 will not operate while this signals stays high. this mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth but cannot provide guaranteed quality over the bluetooth? links. STA2416 d05au1628 wlan STA2416 d05au1626 wlan rf_not_allowed STA2416 general specification 27/38 6.12.3 algorithm 3: bluetooth? master this algorithm represents the symmetrical case of section 6.12.2: algorithm 2: wlan master . also in this case the interface is reduced to 1 line. figure 8. algorithm 3: bluetooth? master when the STA2416 has to operate it alerts high the rf_not_allowed signal and the wlan will not operate while this signals stays high. this mechanism permits to avoid packet collision in order to make an efficient use of the bandwidth, it provides high quality for all bluetooth? links but cannot provide guaranteed quality over the wlan links. 6.12.4 algorithm 4: two-wire mechanism based on algorithm 2 and 3, the host decides, on a case-by-case basis, whether wlan or bluetooth? is master. 6.12.5 algorithm 5: alternatin g wireless medium access (awma) awma utilizes a portion of the wlan beacon interval for bluetooth? operations. from a timing perspective, the medium assignment alternates between usage following wlan procedures and usage following bluetooth? procedures. the timing synchronization between the wlan and the STA2416 is done by the hw signal medium_free. STA2416 d05au1627 wlan rf_not_allowed table 10. wlan hw signal assignment wlan scenario 1: pta scenario 2: wlan master scenario 3: bt master scenario 4: 2-wire scenario 5: awma wlan 1 tx_ confirm bt_rf_not_ allowed not used bt_rf_not_ allowed medium_free wlan 2 tx_ request not used wlan_rf_ not_ allowed wlan_rf_ not_ allowed not used wlan 3 status not used not used not used not used wlan 4 optional_ signal not used not used not used not used interfaces STA2416 28/38 7 interfaces 7.1 uart interface the chip contains two enhanced (128 byte transmit fifo and 128 byte receive fifo, sleep mode, 127 rx and 128 tx interrupt thresholds) uarts named uart1 and uart2 compatible with the standard m16550 uart. for uart1, only rx and tx signals are available (used for debug purposes). uart2 features: standard hci uart transport layer: ? all hci commands as described in the bluetooth? specification 1.1 ? st specific hci command (check STA2416 software interface document for more information) rxd, txd, cts, rts on permanent external pins 128-byte fifos, for transmit and for receive default configuration: 57.600 kbps specific hci command to change to the baud rates given in ta b l e 1 1 7.2 synchronous serial interface the synchronous serial interface (ssi) (or the synchronous peripheral interface (spi)) is a flexible module supporting full-duplex and half-duplex synchronous communications with external devices in master and slave mode. it enables a microcontroller unit to communicate with peripheral devices or allows inter-processor communications in a multiple-master environment. this interface is compatible with the motorola spi standard, with the texas instruments synchronous serial frame format and with national semiconductor microwire standard. special extensions are implemented to support the agilent spi interface for optical mouse applications and the 32-bit data spi for stereo codec applications. table 11. list of supported baud rates baud rate ? 57.600 kbps (default) 4800 921.6k 38.4 k 2400 460.8 k 28.8 k 1800 230.4 k 19.2 k 1200 153.6 k 14.4 k 900 115.2 k 9600 600 76.8 k 7200 300 STA2416 interfaces 29/38 7.2.1 feature descrip tion: agilent mode one application is a combination of a bluetooth? device with an agilent optical mouse sensor to build a bluetooth? mouse. the agilent chip has an spi interface with one bi-directional data port. when spi_io from adns_2030 is driving, spi_rxd should be active, while spi_txd is set as a tri-state high impedance input. for a read operation, the bluetooth? spi_txd is put in high impedance state after the reception of the address. note that this feature works independently of the spi mode, supporting other combinations. in this case, the devices are connected as described in figure 9 . figure 9. agilent mode 7.2.2 feature descr iption: 32-bit spi one application is a bluetooth? stereo headset. in this application, the audio samples are received from the emitter through the air using the bluetooth? baseband with acl packets. the samples are decoded by the embedded arm cpu (the samples were encoded, for compression, in sbc or mp3 format) and then sent to a stereo codec though the spi interface. the application is described in figure 10 . figure 10. 32-bit spi to support this application, the data size is 32 bits. the 32-bit support is implemented for both transmit and receive. STA2416 agilent adns-2030 spi_clk spi_frm spi_txd spi_rxd spi_clk spi_io STA2416 spi slave mode 32 bits stw5094a codec spi master mode 32 bits spi_txd spi_rxd spi_frm spi_clk bluetooth reception stereo headset 32 spi_clk 16 spi_clk interfaces STA2416 30/38 7.3 i 2 c interface used to access i 2 c peripherals. the interface is a fast master i 2 c; it has full control of th e interface at all times. i 2 c slave functionality is not supported. 7.4 usb interface the usb interface is compliant with the usb 2.0 full speed specif ication. max throughput on the usb interface is 12 mbit/s. figure 11 gives an overview of the main components needed for supporting the usb interface, as specified in the bluetooth? core specification. for clarity, the serial interface (including the uart transport layer) is also shown. figure 11. usb interface the usb device registers and fifos are me mory mapped. the usb driver will use these registers to access the usb interface. the equivalent exists for the hci communication over uart. for transmission to the host, the usb and serial drivers interface with the hw via a set of registers and fifos, while in the other direction, the hardware may trigger the drivers through a set of interrupts (identified by the rtos, and directed to the appropriate driver routines). 7.5 jtag interface the jtag interface is complia nt with the jtag ieee std 1 149.1. its allows both the boundary scan of the digital pins and the debug of the arm7tdmi application when connected with the standard arm7 development tools. hci usb transport layer uart transport layer rtos STA2416 hw usb driver serial driver uart device registers fifos usb device registers fifos irq irq d05au1625 STA2416 interfaces 31/38 7.6 rf interface the STA2416 radio interface is compatible to bluerf (unidirectional rxmode2 for data and unidirectional serial interface for control). 7.7 pcm voice interface the voice interface is a direct pcm interface to connect to a standard codec (for example, stw5093 or stw5094) including internal decimator and interpolator filters. the data can be linear pcm (13 to 16-bit), -law (8-bit) or a-la w (8-bit). by default the codec interface is configured as master. the encoding on the air interface is programmable to be cvsd, a-law or -law. the pcm block is able to manage the pcm bus with up to three timeslots. in master mode, pcm clock and data can operate at 2 mhz or at 2.048 mhz to allow interfacing of standard codecs. the four signals of the pcm interface are: directions of pcm_a and pcm_b are software configurable. three additional pcm_sync signals can be provided via the gpios. see chapter 10 on page 35 for more details. figure 12. pcm (a-law, -law) standard mode figure 13. linear mode pcm_clk: pcm clock pcm_sync: pcm 8 khz sync pcm_a: pcm data pcm_b: pcm data d02tl558 pcm_clk pcm_sync pcm_a b b pcm_b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 b 125 s b d02tl559 pcm_clk pcm_sync pcm_a pcm_b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 125 s interfaces STA2416 32/38 figure 14. pcm interface timing table 12. pcm interface timing symbol description min typ max unit pcm interface f pcm_clk frequency of pcm_clk (master) 2048 khz f pcm_sync frequency of pcm_sync 8 khz t wch high period of pcm_clk 200 ns t wcl low period of pcm_clk 200 ns t wsh high period of pcm_sync 200 ns t ssc setup time, pcm_sync high to pcm_clk low 100 ns t sdc setup time, pcm_a/b input valid to pcm_clk low 100 ns t hcd hold time, pcm_clk low to pcm_a/b input invalid 100 ns t dcd delay time, pcm_clk high to pcm_a/b output valid 150 ns d02tl557 pcm_clk t wcl pcm_sync pcm_a/b in pcm_b/a out msb msb-1 msb-2 msb-3 msb-4 msb msb-1 msb-2 msb-3 msb-4 t ssc t wch t wsh t hcd t sdc t dcd STA2416 hci uart transport layer 33/38 8 hci uart transport layer the uart transport layer has been specified by the bluetooth? sig, and allows hci level communication between a host controller (STA2416) and a host (for example, pc), via a serial line. the objective of this hci uart transport layer is to make it possible to use the bluetooth? hci over a serial interface between two uarts on the same pcb. the hci uart transport layer assumes that the uart communication is free from line errors. 8.1 uart settings the hci uart transport layer uses the following settings for rs232: flow control with rts/cts is used to prevent temporary uart buffer overrun. it should not be used for flow control of hci, since hci has its own flow control mechanisms for hci commands, hci events and hci data. if cts is 1, then the host/host controller is allowed to send. if cts is 0, then the host/host co ntroller is not allowed to send. the flow-off response time defines the maximum time from setting rts low until the byte flow actually stops. the signals should be connected in a null-modem fashion; i.e. the local txd should be connected to the remote rxd and the local rts should be connected to the remote cts and vice versa. figure 15. uart transport layer baud rate: configurable (default baud rate: 57.600 kbps) number of data bits: 8 parity bit: no parity stop bit: 1 stop bit flow control: rts/cts flow-off response time: 3 ms bluethooth host bluethooth host controller hci uart transport layer bluethooth hci d02tl55 6 hci usb transport layer STA2416 34/38 9 hci usb transport layer the usb transport layer has been specified by the bluetooth? sig, and allows hci level communication between a host controller (STA2416) and a host (for example, pc), via a usb interface. the usb transport layer is co mpletely implemented in sw. it accepts hci messages from the hci layer, prepares it for transmission over a usb bus, and sends it to the usb driver. it reassembles the hci messages from usb data received from the usb driver, and sends these messages to the hci layer. the transport layer does not interpret the contents (payload) of the hci messages; it only examines the header. STA2416 class1 power support 35/38 10 class1 power support the chip can control an external power amplifier (pa). several signals are duplicated on gpios for this purpose in order to avoid digital/analogue noise loops in the radio. a software controlled register enables the alternate functions of gpio [15:11] [9:6]to generate the signals for driving an external pa in a bluetooth? class1 power application. every bit enables a dedicated signal on a gpio pin, as described in ta b l e 1 3 . the signal brxen is the same as the rx_on output pin. the signal not_brxen is the inverted signal, in order to save components on the application board. pa7 to pa0 are the power amplifier control lines. they are managed, on a connection basis, by the baseband core. the power level programmed for a certain bluetooth? connection is managed by the firmware, as specified in the bluetooth? sig spec. the wlan signals, as described in section 6.12: bluetooth? - wlan coexistence in collocated scenario on page 25 , can be enabled on gipio pins the wxtra pcm sync signals, as described in section 7.7: pcm voice interface on page 31 , can be flexibly configured on gpio pins to connect multiple codecs. table 13. gpios alternate functionalities involved gpio description gpio0 no dedicated function gpio1 wlan 1 gpio2 wlan 2 gpio3 wlan 3 gpio4 wlan 4 gpio5 (used for usb reset pull.) gpio6 power class 1 rx_on gpio7 power class 1 not_rxon gpio8 power class 1 pa0 or pcm sync 1 gpio9 power class 1 pa1 or pcm sync 2 gpio11 power class 1 pa3 gpio12 power class 1 pa4 gpio13 power class 1 pa5 gpio14 power class 1 pa6 gpio15 power class 1 pa7 package information STA2416 36/38 11 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 16. lfbga120 (10x10x1.4mm) mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.40 0.055 a1 0.20 0.008 a2 1 0.039 b 0.25 0.30 0.35 0.010 0.012 0.014 d 9.90 10.00 10.10 0.390 0.394 0.398 d1 8.50 0.335 d2 6.50 0.256 e 9.90 10.00 10.10 0.390 0.394 0.398 e1 8.50 0.335 e2 6.50 0.256 ed 0.50 basic 0.020 basic ee 0.50 basic 0.020 basic fd 0.75 0.029 fe 0.75 0.029 md 18 me 18 n 120 balls se 0.25 basic 0.0098 basic sd 0.25 basic 0.0098 basic tole ranc e aaa 0.15 0.006 bbb 0.10 0.0039 ddd 0.08 0.0031 eee 0.15 0.006 fff 0.05 0.002 lfbga120 low fine ball grid array body: 10 x 10 x 1.4mm 7513355 a STA2416 revision history 37/38 12 revision history table 14. document revision history date revision changes 20-dec-2006 1 initial release. STA2416 38/38 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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